The present invention relates to a semiconductor package with an LSI (Large Scale Integrated circuit) mounted thereon, and a method of producing the same. More particularly, the present invention is concerned with a semiconductor package stack module having LSI chips stacked tridimensionally in a high density, and a method of producing the same.
Various stack module structures for semiconductor packages and methods for producing them are known in the art, as follows.
(1) TSOPs (Thin Small Out line Packages) or similar mold packages are stacked and connected together by leads extending out from the packages (Prior Art 1).
(2) LSI chips are directly stacked together (Prior Art 2). This kind of scheme uses wire bonding, and therefore provides the ends of the chips with a configuration suitable for bonding. The chips are mounted on a carrier substrate a n d connected to the substrate by wires.
(3) Chips connected by TAB (Tape Automated Bonding) are stacked in a module configuration (Prior Art 3). In this case, TAB leads are bent and connected to a carrier substrate.
(4) Semiconductor elements connected by TAB are connected to the islands of a lead frame in a stack, and the entire assembly is sealed by a resin (Prior Art 4).
(5) Japanese Patent Laid-Open Publication No. 61-101067 discloses a memory module structure (Prior Art 5). Specifically, memory ICs are mounted on ceramic packages each having a cavity and formed with electrodes for IC connection and electrodes for chip carrier connection. The electrodes for chip carrier connection are electrically connected to the IC and IC electrodes by thin metallic wires, and the resulting subassembly is sealed by a resin. A plurality of carriers each having an electrode pattern on its outer periphery for leading the electrodes to the outside are stacked. Subsequently, the electrode patterns are electrically connected to each other. The chips are connected by wire bonding while the carriers are connected via the outer walls of a carrier container.
(6) Japanese Patent Laid-Open Publication No. 2-310957 teaches a semiconductor device having a conventional mold package which is provided with leads on its opposite sides, top and bottom (Prior Art 6). A plurality of such semiconductor devices are stacked and connected by leads.
(7) Metal for stack connection is formed on the end faces of semiconductor elements by lithography, oxidation, metal forming or similar technology.
(8) A QFP carrying memory semiconductor elements in a multitip configuration is produced. Such QFPs are stacked and connected by the leads of the QFPs.
(9) Conventional IC packages are stacked and connected by subboards and a mother board.
The prior art technologies described above have the following problems.
(1) Prior Art 1 has a problem that each package has a substantial thickness, resulting in an extremely thick module. Because the chips are connected by wire bonding, the molded configuration is too great to promote miniaturization.
(2) Prior Art 2 must bond the chips one by one, and therefore increases the time and cost for production. Moreover, because bare chips are stacked, the individual chip cannot be tested until the entire module has been assembled. In addition, the ends of the chips must be machined for wire bonding.
(3) Although Prior Art 3 allows a test to be effected with the individual TAB chip, mounting the chips one by one increases the cost. Further, the resulting module is bulky. Because the TAB chips are higher in level than ordinary QFP packages when stacked together, a high packing density is not achievable. In addition, TAB makes various kinds of handling, including mounting, difficult.
(4) Prior Art 4 is expensive, and moreover requires strong semiconductor elements due to the TAB connection. Hence, the semiconductor elements must be provided with a certain thickness and cannot be thinned to below about 0.3 mm. As a result, the entire QFP package cannot be reduced in thickness.
(5) Prior Art 5 also relies on wire bonding. This, coupled with the fact that the carrier containers are connected via their outer walls, increases the size of the module and the wiring length. Further, because each chip carrier has a height more than several times as great as as the thickness of the individual semiconductor device before stacking, the module is not feasible for dense packaging. In addition, connecting the semiconductor devices in multiple stages further lowers the packaging density.
(6) Prior Art 6 disposes a semiconductor element in a mold resin in an inclined position. Hence, the thickness of the mold is several times as greater as the total thickness of the semiconductor element and lead frame. This also obstructs dense packaging. Connecting such semiconductor elements in multiple stages further lowers the packaging density.
(7) Prior Art 7 is technically difficult to practice and needs prohibitive facility investments.
(8) Prior Art 8 is not suitable for dense packaging because the individual QFP package is several times as thick as the semiconductor element. Connecting the packages in multiple stages further lowers the packaging density.
(9) Prior Art 9 simply connects IC packages having the conventional thickness in multiple stages, and therefore fails to enhance dense packaging. In addition, the subboards and mother board further lower the packaging density.